Xgig XGIG6P-PCIE-X16-IOCP3 PCIe 6.0 x16 Analyzer/Exerciser Front End for OCP NIC 3.0

The XGIG6P-PCIE-X16-IOCP3 is the PCIe 6.0 x16 Analyzer/Exerciser front end attachment for OCP NIC 3.0 modules in the VIAVI Xgig EDSFF Analyzer Interposer family. Front end attachments insert into the interposer and can rotate 90 degrees for positioning in the host system.

The Xgig EDSFF Analyzer Interposer installs into an EDSFF or OCP NIC 3.0 slot to provide a fully analog signal path between the root complex and the endpoint. It taps the data signal communication between host and endpoint devices as input to the VIAVI PCIe 6.0 Analyzer/Exerciser chassis, operating at the 64GT/s PCIe 6.0 rate across 16 bi-directional lanes. High-speed linear signal redrivers buffer the system data signals between the slot and the PCB fingers so that a clean signal reaches both the analyzer chassis and the device under test.

In use, the interposer is inserted into the host slot, a DUT carrier is installed into the interposer to create the test data path, and custom data cables connect the interposer to the Analyzer/Exerciser chassis. The analyzer captures tapped DUT data from both the upstream and downstream signal paths. The interposer requires an open DUT system chassis while in use, and its power is independent of the host system.

Together with the VIAVI PCIe 6.0 Analyzer/Exerciser chassis, the interposer supports debug and verification of new ICs and system hardware designs, FPGA firmware, validation of system BIOS and software, and manufacturing test.