Xgig 6P16 16-Lane Analyzer/Exerciser for PCI Express 6.0 with CXL and NVMe Support

The VIAVI Xgig 6P16 is a 16-lane Analyzer/Exerciser for PCI Express 6.0 that extends the Xgig PCIe product portfolio to 64GT/s. Exerciser and Analyzer functionality is provided via a multi-function chassis and application-specific Analyzer or Exerciser Interposers.

Exerciser

The Exerciser provides full, bit-level, repeatable control of generated PCIe 6.0, CXL and NVMe data traffic, which makes it suited to debugging difficult protocol communication problems. It generates PCIe compliant traffic and can be configured to emulate a Root Complex (RC or host system) or an Endpoint (EP) device. Ordered Sets (TS0, TS1, TS2), TLP, DLLP and LTSSM sequences can be defined, transmitted and modified in real time. The 6P16 can also be programmed to generate non-compliant PCIe sequences to test boundary and stress conditions, supporting validation and debug of a PCIe 6.0 controller's state machine and performance tuning of firmware and application software.

Analyzer

The Analyzer gives a detailed view of traffic between a host and an endpoint device, supporting PCIe Flit Mode, Non-Flit Mode, CXL and NVMe. It can alert the user to protocol errors at every layer of the PCIe stack, including state and sub-state errors in the LTSSM Viewer, and detects Flit packing, FEC and CRC errors specific to PCIe 6.0. It pairs with VIAVI function-specific PCIe 6.0 Analyzer Interposers designed to preserve signal integrity; the chassis and interposers are backward compatible with all other PCIe data rates.

Software

The Exerciser and Analyzer work together so that complex test scenarios can be captured and decoded, and bidirectional captures can be saved for analysis in VIAVI tools such as Expert. A scripting API allows custom Exerciser test scripts to be created from scratch or adapted from pre-defined library scripts. The Xgig tools run on a Windows PC.