Xgig XGIG6P-PCIE-X16-IE3 PCIe 6.0 x16 Analyzer/Exerciser Front End EDSFF E3
PCIe 6.0 x16 Analyzer/Exerciser Front End for EDSFF E3 modules, tapping data signals at up to 64GT/s for the VIAVI Xgig Analyzer/Exerciser chassis.
- PCIe generation
- PCIe 6.0
- Maximum data rate
- 64GT/s
- Lane width
- x16
- Form factor
- EDSFF E3 (E3.S / E3.L)
Overview
The XGIG6P-PCIE-X16-IE3 is the PCIe 6.0 x16 Analyzer/Exerciser Front End for EDSFF E3 modules in the VIAVI Xgig EDSFF Analyzer Interposer family. The Analyzer Interposer installs into an EDSFF slot to provide a fully analog signal path between the root complex and the endpoint, and taps the data signal communication between host and endpoint devices for input to the Analyzer/Exerciser chassis. It operates at the 64GT/s PCIe 6.0 rate across 16 lanes (bi-directional).
The interposer uses high-speed linear signal redrivers to buffer system data signals between the PCIe slot and PCB fingers. This design delivers a clean signal to the Analyzer/Exerciser chassis and DUT devices for protocol capture and analysis. Front End Attachments insert into the interposer and can rotate 90 degrees for positioning; an EDSFF DUT Carrier is installed into the interposer to create the test data path, and custom data cables connect the interposer to the VIAVI Protocol Analyzer/Exerciser chassis.
Used with the VIAVI PCIe 6.0 Analyzer/Exerciser chassis, the interposer supports debug and verification of new ICs, new system hardware designs and FPGA firmware, validation of system BIOS and software, and manufacturing test. The Analyzer captures tapped DUT data from both the upstream and downstream signal paths. An open DUT system chassis is required while the interposer is in use.
Key Features
- Operates at 64GT/s PCIe 6.0 data rates, and supports 2.5, 5.0, 8.0, 16 and 32GT/s PCIe data rates
- 16-lane EDSFF 4C/4C+ or 2C slot receptacle accepts all EDSFF endpoint DUT modules
- 16-lane 4C/4C+/2C/1C PCB finger connector installs into the host test system's EDSFF slot
- Supplied with high-quality custom data cables to ensure good signal capture with minimal tuning effort
- x16 version supports up to 4 sets of Analyzer side-band signal triggering and capture
- Analyzer Interposer power is independent of host system
- High-speed linear signal redrivers buffer system data signals between the PCIe slot and PCB fingers
- Front End Attachments can rotate 90 degrees for optimal positioning
- Fully analog signal path between root complex and endpoint
Specifications
| PCIe generation | PCIe 6.0 |
|---|---|
| Maximum data rate |
64GT/s
Also supports 2.5, 5.0, 8.0, 16 and 32GT/s PCIe data rates
|
|
Lane width
XGIG6P-PCIE-X16-IE3
|
x16
16-lanes (bi-directional)
|
|
Form factor
XGIG6P-PCIE-X16-IE3
|
EDSFF E3 (E3.S / E3.L)
Front End EDSFF E3
|
| DUT slot receptacle |
16-lane EDSFF 4C/4C+ or 2C
Accepts all EDSFF endpoint DUT modules
|
| Host connector |
16-lane 4C/4C+/2C/1C PCB finger connector
Installs into host test system's EDSFF slot
|
| Side-band signal triggering and capture |
Up to 4 sets
x16 version
|
| Signal path |
Fully analog signal path between the root complex and the endpoint
High-speed linear signal redrivers buffer system data signals
|
|---|---|
| Power | Analyzer Interposer power is independent of host system |
| Interposer dimensions (WxDxH) | 210 mm x 165 mm x 35 mm |
Specifications are taken from the manufacturer's documentation. See the datasheet for complete and current values.
Applications
- Debug and verification of new ICs
- New system hardware design verification
- FPGA firmware debug
- System BIOS and software validation
- Manufacturing test
- EDSFF E3.S and E3.L module testing
Included
- Kit contents vary by selected products, but typically include cables, cords, brackets and instructions necessary for proper operation
- Custom data cables
Options & Accessories
| Option | Description |
|---|---|
| XGIG6P-PCIE6-X16-AIEE | PCIe 6.0 x16 Analyzer Back End EDSFF |
| XGIG6P-PCIE6-AIE3 | E3.X DUT Carrier |
| XGIG-INTPSR-C-Hx | x-year extended hardware warranty — x = 1, 2, 3, 4 |
